Some microelectronic packages such as those described in commonly assigned U.S. Pat. No. 5,148,265 and 5,148,266, the specifications of which are incorporated by reference herein, may be manufactured by bonding and electrically connecting a plurality of semiconductor chips to a dielectric layer having electrically conductive terminals. In order to protect such microelectronic packages, it is often desirable to encapsulate the microelectronic packages using a polymer, such as an epoxy resin or a silicone elastomer. Such encapsulants are frequently supplied as liquid compositions that must be cured to a solid form. In order to contain the liquid encapsulant composition within the microelectronic package it is sometimes necessary or desirable to laminate a coverlay to the package. The coverlay lamination process seals the package for subsequent encapsulation. One such encapsulation process is describe in commonly assigned U.S. patent application Ser. No. 08/726,697 which was filed on Oct. 7, 1996, the specification of which is incorporated herein by reference.
It is often desirable to laminate a coverlay having a plurality of apertures to the bottom surface of the package so that the terminals are exposed for subsequent connection to an external circuit. The apertures in the coverlay should be aligned with the terminals on the bottom surface of the dielectric layer so that the coverlay seals any holes or windows in the dielectric layer, while the apertures in the coverlay leave the terminals exposed for subsequent attachment of solder balls. With the holes and windows in the dielectric layer covered with the coverlay, the microelectronic package can be encapsulated. Typically this is done with a curable liquid encapsulant composition. The coverlay may then be removed or it may be allowed to remain permanently attached to the microelectronic package.
In order to properly encapsulate the microelectronic package, the bond between the coverlay and the microelectronic package should be void free. Voids can create a number of problems, including solder land contamination, coverlay delamination and poor package aesthetics. If the boundary between the coverlay and the top surface of the microelectronic package contains bubbles or voids, the liquid encapsulant composition can seep through the holes and windows in the dielectric layer and contaminate the solder lands on the surface of the microelectronic package. Delamination is also more likely to start and propagate at voids because the bond between the coverlay and the package at such voids is weak. Voids are also unsightly and may cause a user to question the reliability of the package.
Prior art lamination machines used vacuum, followed by high lamination forces applied directly to the microelectronic package to laminate a coverlay to a microelectronic package. Such machines were used by placing a microelectronic package and coverlay into a vacuum bag. A vacuum was pulled in the bag and then the outside of the vacuum bag was exposed to an elevated pressure. The high forces tended to damage leads in the microelectronic packages. For instance, high lamination forces tend to flatten and kink "S-shaped" leads, leading to a less reliable lead and therefor a less reliable package. Examples of such "S-shaped" leads in microelectronic packaging are described in commonly assigned U.S. Pat. No. 5,398,863, the disclosure of which is incorporated by reference herein.